Conceptual design and testing of new trigger hardware for the ATLAS experiment

Abstract

As our understanding of the Standard Model of particle physics and its described particles and interactions continues to advance, higher centre-of-mass energies and luminosities are required to further drive the research in this field. For the operation of the ATLAS experiment in Run 3 and Run 4, new trigger hardware is designed that meets the increased requirements in terms of input bandwidth and processing capabilities. This enables the use of higher-granularity calorimeter data required to reliably distinguish between separate objects within the detector. This thesis presents the design and verification of the jet Feature Extractor (jFEX), mainly intended for the identification of jets and the calculation of energy sums. This design is based on the latest generation of high-end FPGAs, utilising their available bandwidth and processing capabilities to fulfil the strict boundary conditions of the ATLAS trigger systems. The verification of the design focuses on the densely routed high-speed links, intended for transmission rates of up to 12.8 Gb/s, and an initial estimation of the provided possibilities for new jet trigger algorithms and their performance based on simulated events.