Authors:	Hilder, Janine
Advisor:	Schmidt-Kaler, Ferdinand
Title:	Fault-tolerant quantum error correction with trapped-ion quantum bits
Online publication date:	15-Dec-2022
Year of first publication:	2022
Language:	english
Abstract:	Trapped-ion quantum information processing is among the most promising candidates to realize a scalable quantum computer. A segmented Paul trap can be used to move ions in and out of storage and processing regions via dynamic register reconfiguration operations, enabling effective all-to-all connectivity. The processing region is dedicated to perform laser-driven operations, such as single-qubit rotations and two-qubit entangling gates. To achieve the long-term goal of a large-scale fault-tolerant quantum computer, it is of crucial importance to realize quantum error correction. This thesis focuses on the experimental realization of a fault-tolerant (FT) weight- 4 parity check measurement (PCM) scheme on a trapped-ion quantum processor node. The scheme presented here uses only minimal resource overhead in the form of one additional ’flag’ qubit, to detect errors that would proliferate onto the data qubit register as uncorrectable weight-2 errors. This parity check measurement is an important building block in a broad class of resource-efficient flag-based quantum error correction protocols, such as the topological color code. The experimental result presented is one of the first realizations of the FT PCM scheme on a shuttlingbased trapped-ion quantum computing architecture. A parity measurement fidelity of 92.3(2)% is achieved, which is increased to 93.2(2)% upon flag-qubit conditioning, exceeding the bare parity fidelity by 4.5 standard errors. Injection of bit- and phaseflip errors shows that the scheme is able to reliably intercept faults. For holistic benchmarking, an entanglement witnessing scheme is used, to verify the generation of six-qubit multipartite entanglement, involving all ions participating in the faulttolerant parity measurement. Within the work presented here, improvements of the register reconfiguration operations were carried out, in order to reduce the motional excitation in quantum circuits with a high number of transport, separation/merge and positional ion swap operations, such as the parity measurement scheme. Taking into account the architectural features of the shuttling-based trapped-ion quantum processor, such as effective all-to-all connectivity and no operational crosstalk, the demonstrated building block of flag-based fault-tolerant quantum error correction lays out a clear path towards scalable fault-tolerant quantum computing.
DDC:	530 Physik 530 Physics
Institution:	Johannes Gutenberg-Universität Mainz
Department:	FB 08 Physik, Mathematik u. Informatik
Place:	Mainz
ROR:	https://ror.org/023b0x485
DOI:	http://doi.org/10.25358/openscience-8502
URN:	urn:nbn:de:hebis:77-openscience-8dfa58ee-f1be-46d2-9c79-409d4146e32a5
Version:	Original work
Publication type:	Dissertation
License:	In Copyright
Information on rights of use:	http://rightsstatements.org/vocab/InC/1.0/
Extent:	vii, 148 Seiten ; Illustrationen, Diagramme
Appears in collections:	JGU-Publikationen