Design, implementation and commissioning of the readout and control systems for the Mu3e experiment

Abstract

The Mu3e project is searching for the charged lepton flavour violating muon decay µ+ → e+e−e+. According to the standard model, this decay is suppressed to an unobservable level and detecting it would be a clear sign of new physics. In the absence of a detection, a more precise experimental limit of the branching ratio will impose tighter constraints on beyond standard model theories.

Mu3e phase I is pursuing a challenging branching ratio sensitivity goal of 2 ·10−15. In order to reach this sensitivity, 108 muon decays per second will be observed by a barrel-shaped detector consisting of 2844 monolithic active pixel sensors and 8896 scintillator readout channels.

This thesis has contributed to the data acquisition (DAQ) system of the detector. The DAQ consists of multiple layers and is expected to face a data rate of 100 Gbit/s. It will process this data using a triggerless fast network of FPGAs and GPUs for online track reconstruction. This work has focussed on the lower layers of this system and discusses the development of FPGA hardware structures for readout, control and synchronisation of the Mu3e detector. The functionality of the developed system has been demonstrated in two test runs and insights from these tests have been used to implement DAQ design improvements.